Method for manufacturing multi-level interconnections with dual damascene process

ABSTRACT

Disclosed is a method for manufacturing multi-level interconnections using a dual damascene process. The method includes: forming a first interconnection line on a semiconductor substrate; forming a first interlayer insulating layer on the first interconnection line; forming a first etching stop layer on the first interlayer insulating layer; forming a via hole exposing the first interconnection line by selectively etching the first etching stop layer and the first interlayer insulating layer; forming etching stop patterns around an inlet of the via hole by selectively etching the first etching stop layer; forming a second interlayer insulating layer on the etching stop pattern and the first interlayer insulating layer; forming a trench by selectively etching the second interlayer insulating layer; and forming a conductive layer in the trench and in the via hole.

BACKGROUND

[0001] 1. Technical Field

[0002] A method for manufacturing a semiconductor device is disclosed which includes forming multi-level interconnection lines with a dual damascene process.

[0003] 2. Description of the Related Art

[0004] Recently, with increased integration of a semiconductor device, a limit results in connection with decreasing the line width using a photolithography process, which is used in semiconductor manufacturing processes. To solve the above-mentioned problem, a damascene process has been used.

[0005] Generally, a trench is formed by etching an insulating layer, and a interconnection line is formed in the trench by a self-align dual damascene process.

[0006] In the self-align dual damascene process, a via connecting the lower and upper interconnection lines is aligned at a bottom of the trench. That is, in the self-align dual damascene process, an insulating layer is selectively etched with the photolithography process to form a trench exposing a via at the bottom thereof, and a conductive layer is formed with W, Al or Cu to fill the trench. After that, the conductive layer outside of the trench, namely a portion of the conductive layer, which is not necessarily needed, is removed by an etching or a chemical mechanical polishing (CMP) to form a interconnection line in the trench.

[0007] The above-mentioned self-align dual damascene process is mainly used for forming a bit line, a word line and a metal interconnection line of a dynamic random access memory (DRAM). Specially, by the self-align dual damascene process for forming the trench, a via hole used to form a via connecting upper and interconnection lines, may be formed simultaneously. By the self-align dual damascene process, a height difference due to interconnection lines may not be generated, since the via and interconnection lines are buried in interlayer insulating layers.

[0008]FIGS. 1A to 1D are cross-sectional views illustrating a conventional method for forming a multilevel metal interconnection line according to a conventional self-align dual damascene process.

[0009] Referring to FIG. 1A, interlayer insulating layers 12 and 13 and an etching stop layer 14 are formed on a semiconductor substrate 11. After that, the etching stop layer 14 and the interlayer insulating layer 13 are selectively etched to expose an area where a first metal interconnection line is to be formed.

[0010] Subsequently, a metal layer is deposited on the exposed area and selectively removed to form a metal interconnection line 15 in the etching stop layer 14 and the interlayer insulating layer 13.

[0011] Referring to FIG. 1B, a third interlayer insulating layer 16 is formed on the etching stop layer 14 and the metal interconnection line 15. An etching stop layer 17 and a fourth interlayer insulating layer 18 are successively formed on the third interlayer insulating layer 16, and a photoresist layer (not shown) is formed on the fourth interlayer insulating layer 18, then a via hole mask (not shown) is formed by exposing and developing the photoresist layer.

[0012] Subsequently, the fourth interlayer insulating layer 18, the etching stop layer 17 and the third insulating layer 16 are etched using the via hole mask to form a via hole 19, which exposes a predetermined surface of the metal interconnection line 15.

[0013] Then, after removing the via hole mask, a photoresist layer is formed on the fourth interlayer insulating layer 18 in which the via hole 19 is formed and a trench mask 20, exposing a larger area than the via hole 19, is formed by exposing and developing the photoresist layer.

[0014] Referring to FIG. 1C, a trench 21 is formed by etching the fourth interlayer insulating layer 18 using the trench mask 20. When the trench 21 is formed, the etching is stopped at the etching stop layer 17.

[0015] Referring to FIG. 1D, after removing the trench mask 20, a metal layer is deposited on the resulting structure, then an etch back or a chemical mechanical polishing (CMP) is carried out until the surface of the fourth interlayer insulating layer 18 is exposed, and thereby to form a metal interconnection line 22 in the trench 20. When the metal interconnection line 22 is formed, a via 22 a connected to the metal interconnection line 15 is formed in the via hole.

[0016] As shown in FIG. 2A, after forming the trench by etching the fourth interlayer insulating layer 18, the etching stop layer 17 is left except the via hole region. The etching stop layer 17 is usually formed with the nitride layer having a high capacitance value, in this case, a problem of capacitance increase is occurred due to the remaining etching stop layer 17.

[0017] Also, as shown in FIG. 2B, when the thicknesses of insulating layers are increased, the etch profile on the corner (A) of the trench may be distorted due to the low etch selectivity between the insulating layers formed with the oxide layers and the etching stop layer formed with the nitride layer.

SUMMARY OF THE DISCLOSURE

[0018] A method for forming multi-level interconnection lines using a dual damascene process is disclosed. With the dual damascene process, it is easy to control distortion of a profile on a corner of a trench, and to prevent capacitance value increasing due to a remaining etching stop layer.

[0019] A disclosed method for manufacturing multi-level interconnection lines of semiconductor device comprises: forming a first interconnection line on a semiconductor substrate; forming a first interlayer insulating layer on the first interconnection line; forming a first etching stop layer on the first interlayer insulating layer; forming a via hole exposing the first interconnection line by selectively etching the first etching stop layer and the first interlayer insulating layer; forming etching stop patterns around an inlet of the via hole by selectively etching the first etching stop layer; forming a second interlayer insulating layer on the etching stop pattern and the first interlayer insulating layer; forming a trench by selectively etching the second interlayer insulating layer; and forming a conductive layer in the trench and in the via hole.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Other aspects of the disclosed methods will become apparent from the following description with reference to the accompanying drawings, aherein:

[0021]FIGS. 1A to 1D are cross-sectional views illustrating a conventional method of manufacturing metal interconnection lines using a dual damascene process;

[0022]FIG. 2A is a perspective view illustrating a remaining etching stop layer after etching a trench in accordance with the conventional method;

[0023]FIG. 2B is a perspective view illustrating a profile distortion at a corner of a trench formed in accordance with the conventional method; and

[0024]FIGS. 3A to 3E are cross-sectional views illustrating a method of manufacturing metal interconnection lines using a dual damascene process in accordance with the disclosure.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMODIMENTS

[0025] A method of manufacturing multi-level interconnects using dual damascene process will be described in detail referring to the accompanying drawings.

[0026]FIGS. 3A to 3E are cross-sectional views illustrating a method of manufacturing metal interconnection lines using a dual damascene process.

[0027] Referring to FIG. 3A, in a method of manufacturing multi-level metal interconnection lines, interlayer insulating layers 32 and 33 and an etching stop layer 34 are formed on a semiconductor substrate 31. After that, the etching stop layer 34 and the interlayer insulating layer 33 are selectively etched to exposure a part where a metal interconnection line is to be formed.

[0028] Subsequently, a metal layer is deposited on the exposed part and selectively removed to form a metal interconnection line 35 in the etching stop layer 34 and the interlayer insulating layer 33.

[0029] Referring to FIG. 3B, a third interlayer insulating layer 36 is formed on the etching stop layer 34 and the metal interconnection line 35. An etching stop layer 37 is formed on the third interlayer insulating layer 36. Thereafter, a photoresist layer is coated on the etching stop layer 37 and exposed and developed to form a via hole mask 38.

[0030] The etching stop layers 34 and 37 are formed with any one selected from the group consisting of a nitride layer formed by a plasma enhanced chemical vapor deposition (hereinafter referred as PECVD), a SiON layer, a Ta₂O₅ layer, a ZnO₂ layer, a ZrO₂ layer, a ZnO layer, a HfO layer and an Al₂O₃ layer, at a thickness ranging from about 200 Å to about 3000 Å. Also, the interlayer insulating layers 32, 33 and 36 are formed with any one selected from the group consisting of a spin on glass (SOG) layer, an oxide layer formed with the PECVD method, a tetra ethyl ortho silicate (TEOS) layer, an oxide layer formed with high density plasma (hereinafter referred as HDP), and other insulating layers having a low dielectric constant, at a thickness ranging from about 3000 Å to about 30000 Å.

[0031] Next, the etching stop layer 37 and the third interlayer insulating layer 36 are etched using the via hole mask 38 to form a via hole 39, which exposes a predetermined portion of the metal interconnection line 35.

[0032] Referring to FIG. 3C, after removing the via hole mask 38, another photoresist layer is coated on a resulting structure and is exposed and developed to form a photoresist pattern 40 covering the etching stop layer 37 near the via hole 39. The width d₁ of the photoresist pattern 40 is larger than that of a trench to be formed later, as much as 0.2 μm to 1.0 μm, which is a minimum size of a part needed in an etching process for forming a trench.

[0033] Successively, the etching stop layer 37 is etched using the photoresist pattern as an etch mask to form an etching stop pattern 37 a around the via hole, that is the etching stop pattern 37 a is left at parts where an etching stop layer is needed to form a trench. Therefore, even if the etching stop pattern 37 a is formed with a layer having high dielectric constant, such as a nitrogen layer, the capacitance increase due to the etching stop pattern 37 a may be reduced.

[0034] Referring to FIG. 3D, the etching stop pattern 37 a is exposed by removing the photoresist pattern 40, and a fourth interlayer insulating layer 41 is formed on a resulting structure.

[0035] The fourth interlayer insulating layer 41 is formed with any one selected from the group consisting of a HDP-USG layer, an undoped silicate layer deposited by the HDP, and an oxide layer deposited by the PECVD method or low pressure chemical vapor deposition method (LPCVD), and the fourth interlayer insulating layer 41 is formed at a thickness ranging from about 2000 Å to about 30000 Å, in order to form a void (B) is formed in the via hole 39.

[0036] After forming the fourth interlayer insulating layer 41, a photoresist layer is coated on the fourth interlayer insulating layer 41, and a trench mask 42 is formed by exposing and developing the photoresist layer. At this time, the width d₂ of the trench defined by the trench mask 42 is narrower than that of the via hole, that is spacing between the etching stop layer patterns 37 a.

[0037] Referring to FIG. 3E, a trench is formed by etching the fourth interlayer insulating layer 41 using the trench mask 42 as an etch mask. At this time, the etching is stopped at the etching stop layer patterns 37 a. The etching target may be decreased as much as the size of the void (B) generated in the formation of the fourth insulating layer 41.

[0038] After removing the trench mask 42, a metal layer is deposited on the resulting structure, and an etch back or a chemical mechanical polishing (CMP) is performed until the surface of the fourth interlayer insulating layer 36 is exposed to form a metal interconnection line 43 in the trench, ant at the same time a via 43 a, connecting the metal interconnection line 43 to the metal interconnection line 35, is formed in the via hole 39.

[0039] The metal interconnection lines 35 and 43 and the via 43 a may be formed with any one selected from the group consisting of Al, Cu, Au, Ag and Cr. The metal layers are deposited at a thickness ranging from about 2000 Å to about 30000 Å by using any one selected the group consisting of a chemical vapor deposition (CVD), an electroless deposition and a physical vapor deposition (PVD).

[0040] Meanwhile, before forming the metal interconnection line 43, a diffusion barrier layer may be formed at a thickness ranging from about 1000 Å to about 5000 Å. The diffusion barrier layer is formed with any one selected from the group consisting of a TiN layer, a Ti layer, a W layer, a WN layer and a TiW layer is deposited

[0041] In the above-mentioned embodiments the disclosed method is for forming a multi-layer metal interconnection line. However, the disclosed method may be adapted in a method for forming a word line, a bit line and a contact, which have a dual damascene structure.

[0042] The disclosed method may prevent increasing of a capacitance value by remaining an etching stop layer for forming trench and decreasing etching target by etching a interlayer insulating layer where a void is already formed, so that a margin of a trench etching process may be maximized.

[0043] Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. 

What is claimed is:
 1. A method for manufacturing multi-level interconnection lines of semiconductor device comprising: forming a first interconnection line on a semiconductor substrate; forming a first interlayer insulating layer on the first interconnection line; forming a first etching stop layer on the first interlayer insulating layer; forming a via hole exposing the first interconnection line by selectively etching the first etching stop layer and the first interlayer insulating layer; forming etching stop patterns around an inlet of the via hole by selectively etching the first etching stop layer; forming a second interlayer insulating layer on the etching stop pattern and the first interlayer insulating layer; forming a trench by selectively etching the second interlayer insulating layer; and forming a conductive layer in the trench and in the via hole.
 2. The method of claim 1, wherein the method further comprises: forming a photoresist pattern around the inlet of the via hole to cover portions of the first etching stop layer; and removing other portions of the first etching stop layer which are not covered with the photoresist pattern, whereby the etching stop patterns are formed.
 3. The method of claim 1, wherein the method further comprises: forming a third interlayer insulating layer on the semiconductor substrate; forming a second etching stop layer on the third interlayer insulating layer; pattering the second etching stop layer and the third interlayer insulating layer to expose an opening; and forming a conductive layer in the opening whereby the first interconnection line is formed.
 4. The method of claim 1, wherein the trench exposes portions of the etching stop patterns at the bottom thereof.
 5. The method of claim 1, wherein the width of the trench is wider than that of the via hole.
 6. The method of claim 1, wherein a void is formed within the via hole in the step of forming the second interlayer insulating layer.
 7. The method of claim 6, wherein the second interlayer insulating layer is formed with any one selected from the group consisting of an USG layer deposited by the high density plasma, an oxide deposited by plasma enhance chemical vapor deposition method or low pressure chemical vapor deposition.
 8. The method of claim 6, wherein the second interlayer insulating layer is formed at a thickness ranging from about 3000 Å to about 30000 Å.
 9. The method of claim 1, wherein the first interlayer insulating layer is formed with any one selected from the group consisting of a spin on glass layer, an oxide layer deposited by a plasma enhance chemical vapor deposition method, an oxide layer deposited by a high density plasma method and a tetraethyl-ortho-silicate (TEOS) layer.
 10. The method of claim 9, the first interlayer insulating layer is formed at a thickness ranging from about 2000 Å to about 30000 Å.
 11. The method of claim 1, wherein the first etching stop layer is formed with any one selected from the group consisted of a nitride layer deposited by a plasma enhance chemical vapor deposition method, a SiON layer, a Ta₂O₅ layer, a ZnO₂ layer, a ZrO₂ layer, a ZnO layer, a HfO layer and an Al₂O₃ layer.
 12. The method of claim 11, wherein the first etching stop layer is formed at a thickness ranging from about 200 Å to about 3000 Å.
 13. The method of claim 1, wherein the first interconnection line is formed of any one selected form a group consisting of Al, Cu, Au, Ag and Cr.
 14. The method of claim 1, the first interconnection line is formed at a thickness ranging from about 2000 Å to about 30000 Å.
 15. A Semiconductor device made in accordance with the method of claim
 1. 16. A Semiconductor device made in accordance with the method of claim
 2. 17. A Semiconductor device made in accordance with the method of claim
 3. 18. A Semiconductor device made in accordance with the method of claim
 7. 19. A Semiconductor device made in accordance with the method of claim
 9. 20. A Semiconductor device made in accordance with the method of claim
 11. 